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[PAM 2023] Call for participation
by Marcel Flores 02 Mar '23

02 Mar '23

Hi All, Registration for PAM 2023 is now open and notably free of charge: https://pam2023.networks.imdea.org/registration/ The conference will be held virtually on 21-23 March. This year's program features a range of measurement topics, including applications, performance, network infrastructure and topology, measurement tools, and security and privacy. This year will also include two exciting keynote presentations from Roya Ensafi (University of Michigan) and Andra Lutu (Telefonica Research). The full program and schedule is available here: https://pam2023.networks.imdea.org/program/ We hope you'll join us! -PAM 2023 Organizers

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RACI: Apply for RIPE 86 and RIPE NCC Days Sofia
by Jelena Cosic 01 Mar '23

01 Mar '23

Dear colleagues, hope you're all doing well. The application round for SEE 11 has been closed and the final selection of successful candidates has been made. Congratulations for those selected and say thank you to all that sent their proposals in. If your application was locally relevant but hasn't been selected, don't give up just yet - we have more events lined up! ------------------------------------------------------ NEW MEETING ADDED TO THE RACI APPLICATION CALENDAR ------------------------------------------------------ It is my pleasure to announce that RIPE NCC will be organising another event in the SEE region. The meeting will be held in Sofia, Bulgaria on June 27-28. It will be an opportunity for the technical community in Bulgaria and broader SEE community to come together and share knowledge and experiences, and to identify areas for regional cooperation. The event is open to all and there is no cost to attend. RIPE NCC will be supporting the academic participation through RACI programme once again. The RACI call for application is already open, please apply before April 23: https://www.ripe.net/participate/ripe/raci/raci For people that have already applied for SEE11 and/or RIPE 86, please submit your application details again and only tick the "RIPE NCC Days Sofia" box when doing so. MEETING: RIPE NCC Days Sofia DATE: 27-28 June 2023 RACI APPLICATION FORM: https://www.ripe.net/participate/forms/apply/raci-application-form-2023/ RACI DEADLINE: 23 April 2023 ----------------------------------------------------------------------- RIPE 86 REGISTRATION OPEN & RACI RIPE 86 APPLICATION ROUND CLOSES SOON ----------------------------------------------------------------------- Registration for the RIPE meeting is officially open : https://ripe86.ripe.net/attend/register/ If you work in academia and have an interesting research you want to present to the RIPE community, you still have a week to apply for the RACI programme - applications will be closed on March 9 at 23:59 UTC+1. MEETING: RIPE 86, Rotterdam DATE: 22-26 May 2023 RACI APPLICATION FORM: https://www.ripe.net/participate/forms/apply/raci-application-form-2023/ RACI DEADLINE: 9 March 2023 If you are member of RIPE community interested in attending RIPE meeting but do not have a research ready for a presentation, you can apply to join us as a fellow via RIPE Fellowship programme. The Programme provides basic assistance for successful candidates to participate in a RIPE Meeting. It is open to all in the RIPE NCC service region and might be especially interesting for students. As mentioned, the selected candidates will get a chance to join us for the meeting but unlike RACI, they do not have the opportunity to present their work to the community and that is what distinguishes these two initiatives. The RIPE Fellowship is still a great way to get involved with the RIPE Community. If you know anyone that might be interested, please let them know about this opportunity. The application deadline is the same as for RACI: March 9 at 23:59 UTC+1. More information on Fellowship programme and how to apply here: https://www.ripe.net/participate/ripe/ripe-fellowship If you have any questions about RACI or Fellowship, please feel free to contact me. Kind regards, Jelena

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ISLPED 2023 CALL FOR PAPERS
by Linghao Song 23 Feb '23

23 Feb '23

INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN (ISLPED) 2023 --- ISLPED 2023 CALL FOR PAPERS --- http://www.islped.org <http://www.islped.org/>, Twitter: @islped Conference date: August 7–8, 2023 Location: TU Wien, Vienna, Austria IMPORTANT DATES Abstract registration: March 6, 2023, at 11:59pm PST Full paper: March 13, 2023, at 11:59pm PST Invited Talk, Panel, and Embedded Tutorial Proposals: April 10, 2023 Notification of Paper Acceptance: May 22, 2023 Submission of Camera-Ready Papers: June 19, 2023 The International Symposium on Low Power Electronics and Design (ISLPED) is the premier forum for presentation of innovative research in all aspects of low power electronics and design, ranging from process technologies and analog/digital circuits, simulation and synthesis tools, AI/ML-enhanced EDA/CAD, system-level design, and optimization, to system software and applications. Specific topics include, but are not limited to, the following three main tracks and sub-areas: 1. Technology, Circuits, and Architecture 1.1. Technologies Low-power technologies for device, interconnect, logic, memory, 2.5/3D, cooling, harvesting, sensors, optical, printable, biomedical, battery, and alternative energy storage devices and technology enablers for non-Boolean and quantum/quantum-inspired compute models. 1.2. Circuits Low-power circuits for logic, memory, reliability, yield, clocking, resiliency, near-/sub-threshold, and assist schemes; Low-power analog/mixed-signal circuits for wireless, RF, MEMS, AD/DA Converters, I/O, PLLs/DLLS, imaging and DC-DC converters; Energy-efficient circuits for emerging applications (e.g., biomedical, in-vitro sensing, autonomous), circuits using emerging technologies; Cryogenic circuits. Design technology co-optimization (DTCO) for low power. 1.3. Logic and Architecture Low-power logic and microarchitecture for SoC designs, processor cores (compute, graphics, and other special purpose cores), cache, memory, arithmetic/signal processing, cryptography, variability, asynchronous design, and non-conventional computing. System technology co-optimization (STCO) for low power. 2. EDA, Systems, and Software 2.1. CAD Tools and Methodologies CAD tools, methodologies, and AI/ML-based approaches for low-power and thermal-aware design. AI/ML for acceleration of circuit simulation and IP block design convergence. Power estimation, optimization, reliability, and variation impact on power optimization at all levels of design abstraction: physical, circuit, gate, register transfer, behavior, and algorithm. 2.2. Systems and Platforms Low-power, power-aware, and thermal-aware system design including data centers, SoCs, embedded systems, Internet-of-Things (IoT), wearable computing, body-area networks, wireless sensor networks, and system-level power implications due to reliability and variability. Applications of AI/ML-based solutions and brain-inspired computing to power-aware system and platform design. 2.3. Software and Applications Energy-efficient, energy/thermal-aware software and application design, including scheduling and management, power optimization through HW/SW codesign, and emerging low-power AI/ML applications. 3. Crosscutting Topics 3.1. AI/ML Hardware Low-power AI/ML HW techniques including approximations, application driven optimizations, in-memory/energy-efficient accelerations, and neuromorphic computing; Energy-efficient AI/ML HW using emerging technologies (including quantum computing). 3.2. Hardware and System Security Low-power hardware security primitives (PUF, TRNG, cryptographic/post-quantum cryptographic accelerators), nano-electronics security, supply chain security, IoT security and AI/ML security; Energy-efficient approaches to system security. 4. Industrial Design Track ISLPED’23 solicits papers for an “Industrial Design” track to reinforce interaction between the academic research community and industry. Industrial Design track papers have the same submission deadline as regular papers and should focus on similar topics but are expected to provide a complementary perspective to academic research by focusing on challenges, solutions, and lessons learnt while implementing industrial-scale designs. Submissions (not published/accepted/under review by another journal, conference, symposium, or workshop) should be full-length papers of up to 6 pages (PDF format, double-column, US letter size, using the IEEE Conference format, available at (https://www.ieee.org/conferences/publishing/templates.html) including all illustrations, tables, references, and an abstract of no more than 250 words. Submissions must be anonymous. Submissions failing above requirements will be automatically rejected. Accepted papers will be submitted to the IEEE Xplore Digital Library and the ACM Digital Library. ISLPED’23 will present three Best Paper Awards based on the ratings of reviewers and a panel of judges. ISLPED also features a Low Power Design Contest with live demonstrations and awards. Submissions are due on May 15, 2023. More details will soon be available on the conference web page. There will be several invited talks by industry and academic thought leaders on key issues in low power electronics and design. The Symposium may also include embedded tutorials to provide attendees with the necessary background to follow recent research results, as well as panel discussions on future directions in low power electronics and design. Proposals for invited talks, embedded tutorials, and panels should be sent by email to the ISLPED’23 Technical Program Co-Chairs, Umit Ogras (uogras(a)wisc.edu <mailto:uogras@wisc.edu>) and Pascal Meinerzhagen (pascal.a.meinerzhagen(a)intel.com <mailto:pascal.a.meinerzhagen@intel.com>) by the deadline listed above. Participants interested in exhibiting at the Symposium should contact the General Co-Chairs by May 1, 2023.

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ACM EdgeSys'23 Call for Submissions
by Aaron Ding 06 Feb '23

06 Feb '23

For RACI colleagues, ACM EdgeSys'23 is calling for submissions. ****************************************************************** https://edge-sys.github.io/2023/ ****************************************************************** IMPORTANT DATES • Submission deadline: 10 March 2023 • Acceptance notification: 10 April 2023 • Camera ready: 16 April 2023 • EdgeSys date: 8 May 2023 ****************************************************************** EdgeSys'23 aims to bring together system researchers, data scientists, engineers and practitioners to identify open directions and discuss the latest research ideas and results on edge systems, analytics and networking, especially those related to novel and emerging technologies and use cases. EdgeSys focuses on systems, analytics and networking aspects, covering system architecture, distributed ML algorithms, decentralized networking, distributed consensus and ledger techniques, edge services and data analysis. The topics include but are not limited to the following: • System Architecture for Edge Computing • Serverless, In-network Computing • Edge Storage Systems • Distributed Machine Learning for Edge Analytics and Services • Edge-driven Data Analytics • Lightweight Virtualization for Edge Computing • Distributed Consensus Algorithms and Ledger Technologies • Infrastructure and Toolkit for Edge AI • Trustworthy Edge AI • Sustainable Edge Computing • IoT Networking and Communications • (Autonomous) Management for Edge Systems • System Performance and Measurement • Security and Trust Management • Privacy-Preserving Analytics • Data Provenance for Distributed Processing • Heterogeneous & Scalable Orchestration • Joint Optimization of Network, Computation and Storage Resources ****************************************************************** INSTRUCTIONS FOR PAPER SUBMISSION Authors are encouraged to submit papers describing original and unpublished research, not currently under review in other venues. In particular, innovative, early-stage ideas and preliminary results are welcome. Papers must be submitted electronically as PDF files, formatted for 8.5x11-inch paper. The length of the paper must be no more than 6 pages in the ACM double-column format (10-pt font), including references and everything. Authors are suggested to use the ACM Master article template. The reviews will be single blind. The first page must contain an abstract, the name(s) and affiliation(s) of the author(s), as well as the corresponding contact information. Each submission will receive independent, blind peer reviews from the program committee. Accepted papers will be published in the ACM Digital Library. At least one of the authors of every accepted paper must register and present the paper at the workshop. The program committee will elect one paper for the Best Paper Award. Submission: https://edgesys23.hotcrp.com/ ****************************************************************** EdgeSys Chairs • Aaron Ding (TU Delft, Netherlands) • Ella Peltonen (University of Oulu, Finland) • Volker Hilt (Nokia Bell Labs, Germany) Steering Committee • Jon Crowcroft (University of Cambridge, UK) • Henning Schulzrinne (Columbia University, USA) • Steve Uhlig (Queen Mary University of London, UK) • Dirk Kutscher (HKUST, Hong Kong SAR) • Dieter Kranzlmüller (University of Munich | LRZ, Germany) • Peter Pietzuch (Imperial College London, UK) Aaron

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ISLPED 2023 CALL FOR PAPERS
by Linghao Song 27 Jan '23

27 Jan '23

INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN (ISLPED) 2023 --- ISLPED 2023 CALL FOR PAPERS --- http://www.islped.org <http://www.islped.org/>, Twitter: @islped Conference date: August 7–8, 2023 Location: TU Wien, Vienna, Austria IMPORTANT DATES Abstract registration: March 6, 2023, at 11:59pm PST Full paper: March 13, 2023, at 11:59pm PST Invited Talk, Panel, and Embedded Tutorial Proposals: April 10, 2023 Notification of Paper Acceptance: May 22, 2023 Submission of Camera-Ready Papers: June 19, 2023 The International Symposium on Low Power Electronics and Design (ISLPED) is the premier forum for presentation of innovative research in all aspects of low power electronics and design, ranging from process technologies and analog/digital circuits, simulation and synthesis tools, AI/ML-enhanced EDA/CAD, system-level design, and optimization, to system software and applications. Specific topics include, but are not limited to, the following three main tracks and sub-areas: 1. Technology, Circuits, and Architecture 1.1. Technologies Low-power technologies for device, interconnect, logic, memory, 2.5/3D, cooling, harvesting, sensors, optical, printable, biomedical, battery, and alternative energy storage devices and technology enablers for non-Boolean and quantum/quantum-inspired compute models. 1.2. Circuits Low-power circuits for logic, memory, reliability, yield, clocking, resiliency, near-/sub-threshold, and assist schemes; Low-power analog/mixed-signal circuits for wireless, RF, MEMS, AD/DA Converters, I/O, PLLs/DLLS, imaging and DC-DC converters; Energy-efficient circuits for emerging applications (e.g., biomedical, in-vitro sensing, autonomous), circuits using emerging technologies; Cryogenic circuits. Design technology co-optimization (DTCO) for low power. 1.3. Logic and Architecture Low-power logic and microarchitecture for SoC designs, processor cores (compute, graphics, and other special purpose cores), cache, memory, arithmetic/signal processing, cryptography, variability, asynchronous design, and non-conventional computing. System technology co-optimization (STCO) for low power. 2. EDA, Systems, and Software 2.1. CAD Tools and Methodologies CAD tools, methodologies, and AI/ML-based approaches for low-power and thermal-aware design. AI/ML for acceleration of circuit simulation and IP block design convergence. Power estimation, optimization, reliability, and variation impact on power optimization at all levels of design abstraction: physical, circuit, gate, register transfer, behavior, and algorithm. 2.2. Systems and Platforms Low-power, power-aware, and thermal-aware system design including data centers, SoCs, embedded systems, Internet-of-Things (IoT), wearable computing, body-area networks, wireless sensor networks, and system-level power implications due to reliability and variability. Applications of AI/ML-based solutions and brain-inspired computing to power-aware system and platform design. 2.3. Software and Applications Energy-efficient, energy/thermal-aware software and application design, including scheduling and management, power optimization through HW/SW codesign, and emerging low-power AI/ML applications. 3. Crosscutting Topics 3.1. AI/ML Hardware Low-power AI/ML HW techniques including approximations, application driven optimizations, in-memory/energy-efficient accelerations, and neuromorphic computing; Energy-efficient AI/ML HW using emerging technologies (including quantum computing). 3.2. Hardware and System Security Low-power hardware security primitives (PUF, TRNG, cryptographic/post-quantum cryptographic accelerators), nano-electronics security, supply chain security, IoT security and AI/ML security; Energy-efficient approaches to system security. 4. Industrial Design Track ISLPED’23 solicits papers for an “Industrial Design” track to reinforce interaction between the academic research community and industry. Industrial Design track papers have the same submission deadline as regular papers and should focus on similar topics but are expected to provide a complementary perspective to academic research by focusing on challenges, solutions, and lessons learnt while implementing industrial-scale designs. Submissions (not published/accepted/under review by another journal, conference, symposium, or workshop) should be full-length papers of up to 6 pages (PDF format, double-column, US letter size, using the IEEE Conference format, available at (https://www.ieee.org/conferences/publishing/templates.html) including all illustrations, tables, references, and an abstract of no more than 250 words. Submissions must be anonymous. Submissions failing above requirements will be automatically rejected. Accepted papers will be submitted to the IEEE Xplore Digital Library and the ACM Digital Library. ISLPED’23 will present three Best Paper Awards based on the ratings of reviewers and a panel of judges. ISLPED also features a Low Power Design Contest with live demonstrations and awards. Submissions are due on May 15, 2023. More details will soon be available on the conference web page. There will be several invited talks by industry and academic thought leaders on key issues in low power electronics and design. The Symposium may also include embedded tutorials to provide attendees with the necessary background to follow recent research results, as well as panel discussions on future directions in low power electronics and design. Proposals for invited talks, embedded tutorials, and panels should be sent by email to the ISLPED’23 Technical Program Co-Chairs, Umit Ogras (uogras(a)wisc.edu <mailto:uogras@wisc.edu>) and Pascal Meinerzhagen (pascal.a.meinerzhagen(a)intel.com <mailto:pascal.a.meinerzhagen@intel.com>) by the deadline listed above. Participants interested in exhibiting at the Symposium should contact the General Co-Chairs by May 1, 2023.

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Postdoc position 12-24 months Ressource allocation and Machine learning for network slicing
by Isabel AMIGO 24 Jan '23

24 Jan '23

Dear all We are urgently seeking for a motivated candidate to fulfill our available post-doc position on RA and AIML tools for slicing in the context of 5G/B5G networks. What will you be doing: * Contribute to the project through research activities through one or several following three axes, according to your profile: * Model-Based Resource Allocation Mechanisms: This axis focuses on analytical methods to solve the problem of on-demand resource allocation. * Mechanisms of data-based resource allocation: this axis focuses on AIML methods in order to solve the problems formulated in the previous point * Model and integration. This axis will focus on the implementation of the algorithms designed by previous axes in an existing testbed * Possibility of scientific travels to project partners in South America Profile's requirements: * PhD less than 3 years old in Computer Science, Applied Mathematics or equivalent. * Capacity for synthesis, reporting and communication * Autonomy * Ability for teamwork * Excellent written English What would be a plus in your profile: * Good computer skills (eg Python, PyTorch OpenAI Gym). * Solid mathematical knowledge and experience in stochastic modeling and/or resource allocation issues * Knowledge of data networks * Knowledge and experience in AIML techniques * Skills and experience in experimentation on optical networks would be a plus but are not essential Duration: 12 months with possibility to extend to 24 months Location: the postdoc will work in a joint team including researchers from different groups at the Computer Science department, Optics department, and Networking and Security department of IMT Atlantique, France. The post doc will be based either at the Brest or Rennes campus. For more information and to apply, please visit [*] , or answer to this e-mail if further questions, before February 16th. Thanks in advance if you can spread the word, and sorry if you've received this message multiple times! Kind regards, -- Isabel AMIGO +33 (0)2 29 00 14 21 IMT Atlantique, Dpt. Info [ https://www.imt-atlantique.fr/fr/personne/isabel-amigo | https://www.imt-atlantique.fr/fr/personne/isabel-amigo ] [*] https://institutminestelecom.recruitee.com/l/en/o/postdoctorante-ou-postdoc…

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REMINDER: RACI - Call for Applications for SEE 11 is closing soon
by Jelena Cosic 18 Jan '23

18 Jan '23

Dear colleagues, we are half way through the RACI application round for the upcoming RIPE NCC regional meeting SEE 11 in Split, Croatia. If you are working on something interesting, please apply soon! As always, if you know someone in your network who is, please forward them this message. The deadline for application is *January 29th*. More details below. To apply submit a short abstract and draft slides via: https://www.ripe.net/raci --------------------- Application deadlines --------------------- SEE 11 (4-5 April, Split): apply by 29 January 2023 RIPE 86 (22-26 May, Rotterdam): apply by 9 March 2023 --------------------------- Examples of relevant topics --------------------------- - Network measurements and analyses - IPv6 deployment - BGP routing - Network security - Internet governance - Peering and interconnectivity - Internet of Things - Sustainability in ICT ------------------------------------------------- Get the latest news on RACI and Internet research ------------------------------------------------- - Subscribe to the RACI mailing list: https://www.ripe.net/raci/mailing-list - Join our group on LinkedIn: https://www.ripe.net/raci/linkedin Please let me know if you have any questions. Kind regards, Jelena

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CfP -- 2nd Int. Workshop on Green and Sustainable Networking (GreenNet 2023)
by Vesna Manojlovic 12 Jan '23

12 Jan '23

For Your Information On 19/12/2022 01:52, Hesham ElBakoury wrote: > > *2nd Int. Workshop on Green and Sustainable Networking (GreenNet 2023)* > > Co-located with IEEE ICC > > 28. May - 01. June 2023 > > Rome, Italy > > https://icc2023.ieee-icc.org/workshop/ws-07-2nd-workshop-green-and-sustaina… > > *Important Dates* > > ============== > > *Paper Submission Deadline: *January 20, 2023 > > *Acceptance Notification: *March 06, 2023 > > *Camera Ready: *March 15, 2023 > > *Registration for Accepted Papers: *March 15, 2023 > > *Workshop Date: *May 28 or June 01, 2023 > > EDAS submission link: https://edas.info/newPaper.php?c=30418 > > *Motivation* > > ========== > > Energy efficiency and sustainability have become of paramount importance > in all human activities. Regarding ICT, it has been long recognized that > its impact on helping reduce the carbon footprint of other activities > can be significant; then, it would be odd if the same principle would > not apply to ICT itself. In particular, computing, communications and > networking are relevant activities in this context, whose impact is > absolutely non-negligible. The concept of Green Computing and Networking > is currently gaining additional momentum with the growth in the number > of networked applications in all vertical sectors, in the number of > users and in the amount of traffic they generate. The pervasiveness of > mobile networks in 5G and their evolution toward 6G, the spreading of > edge computing and micro-data centers and the demand in computational > and data transport capacity across the edge-cloud continuum are all > factors that further contribute to making energy efficiency a > fundamental aspect of future networks. > > ** > > *Goals* > > ========== > > The goal of the GreenNet Workshop is to address emerging concepts and > challenges related to energy efficiency and sustainability for networked > services, by pursuing sustainability in the context of ongoing > developments such as 5G and beyond, 6G, usage of AI/ML or distributed > ledger solutions and with different network access technologies. To this > aim, the Workshop will also address advanced traffic and power models, > as well as management and control strategies, along with Application > Programming Interfaces (APIs), to be used for the lifecycle management > and optimization of Physical and Virtual Network Functions, the creation > and dynamic reconfiguration of network slices, and the balance between > sustainability in terms of energy efficiency and performance. > Furthermore, the goal is to not only consider an energy efficient and > sustainable access network but complete network, monitoring, and > management solutions from data generation to data processing and further > usage The trade-off between availability, resiliency, programmability, > and energy efficiency is a key challenge. Monitoring methods and metrics > for power consumption, energy efficiency, as well as sustainability are > important, as well as benchmarking of solutions based on well-defined KPIs. > > > We solicit original papers on the following (and related) topics > > > *Topics of Interest* > > ================= > > Authors are invited to submit original contributions (written in > English) in PDF format. Only original papers not published or submitted > for publication elsewhere will be considered for the workshop. Only PDF > files will be accepted for the review process and all manuscripts must > be electronically submitted through EDAS. > > > ● Traffic modeling and prediction for performance and power representation > > ○ Analytical models of network power consumption > > ○ Accuracy and granularity of traffic prediction models and BS/MS power > consumption models > > ●. Management and control mechanisms for the dynamic optimization of the > trade-off between power, energy efficiency, sustainability and > performance, availability, resilience > > ○ APIs for power management interfaces > > ○ Sleep modes in RAN/O-RAN and core networks > > ○ Timing and scheduling of hardware sleep modes in the access and backhaul > > ○ Orchestration of sleep modes > > ○ Decentralized energy management, e.g., using distributed ledger > technologies blockchain > > ● Benchmarking of solutions w.r.t. energy efficiency and sustainability > based on KPIs > > ● Sensor and industrial automation networks > > ● Evolutionary strategies for the achievement of 6G energy-efficiency > KPIs and Quality of Information improvement > > ● AI/ML techniques for power and performance management in virtualized > environments > > ● AI/ML for slicing energy efficiency, fog/cloud MEC virtualization, > self-x technologies, adaptation, automation, and zero-touch > > ● Architectural solutions toward network sustainability > > ○ Use of renewable energy by network infrastructure devices to reduce > network carbon footprint > > ○ Power-aware network slicing > > ○ Role of software in reducing network energy consumption and carbon > footprint > > ○ Role of the edge to support energy sustainable infrastructure > > ● Energy-efficiency and sustainability in all parts of networked services > > ○ Wired and wireless energy efficiency > > ○ Energy-saving Internet protocols > > ○ Energy efficiency and carbon neutrality in the fog/MEC/cloud continuum > > ○ Energy efficient internetworking of mobile backhaul/core and remote > data centers > > ○ Energy-efficient 3D networks > > ● Multi-technology solutions > > ○ Mutual roles in energy saving of satellite and terrestrial networks > > ○ Multipath support over multiple wireless technologies for access > traffic steering, switching, splitting (ATSS) > > ● Coping with the end of Moore’s law > > ● Role of standardization including network energy efficiency and > sustainability metrics > > > *Workshop Chairs* > > ================ > > Roberto Bruschi, University of Genoa and CNIT S2N National Lab, Italy > (roberto.bruschi(a)unige.it) > > Franco Davoli, University of Genoa and CNIT S2N National Lab, Italy > (franco.davoli@unigeit <mailto:franco.davoli@unige.it>) > > Hesham ElBakoury, Futurewei Technologies, Santa Clara, CA, USA > (helbakoury(a)gmail.com) > > Timothy O'Farrell, University of Sheffield, UK (t.ofarrell(a)sheffield.ac.uk) > > Tobias Hoßfeld, University of Würzburg, Germany > (tobias.hossfeld(a)uni-wuerzburg.de) > > Frank Loh, University of Würzburg, Germany (frank.loh(a)uni-wuerzburg.de > <mailto:frank.loh@uni-wuerzburg.de>) > > > > -- Senior Community Builder, RIPE NCC https://labs.ripe.net/author/becha/

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ISLPED 2023 CALL FOR PAPERS
by Linghao Song 11 Jan '23

11 Jan '23

INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN (ISLPED) 2023 --- ISLPED 2023 CALL FOR PAPERS --- http://www.islped.org <http://www.islped.org/>, Twitter: @islped Conference date: August 7–8, 2023 Location: TU Wien, Vienna, Austria IMPORTANT DATES Abstract registration: March 6, 2023, at 11:59pm PST Full paper: March 13, 2023, at 11:59pm PST Invited Talk, Panel, and Embedded Tutorial Proposals: April 10, 2023 Notification of Paper Acceptance: May 22, 2023 Submission of Camera-Ready Papers: June 19, 2023 The International Symposium on Low Power Electronics and Design (ISLPED) is the premier forum for presentation of innovative research in all aspects of low power electronics and design, ranging from process technologies and analog/digital circuits, simulation and synthesis tools, AI/ML-enhanced EDA/CAD, system-level design, and optimization, to system software and applications. Specific topics include, but are not limited to, the following three main tracks and sub-areas: 1. Technology, Circuits, and Architecture 1.1. Technologies Low-power technologies for device, interconnect, logic, memory, 2.5/3D, cooling, harvesting, sensors, optical, printable, biomedical, battery, and alternative energy storage devices and technology enablers for non-Boolean and quantum/quantum-inspired compute models. 1.2. Circuits Low-power circuits for logic, memory, reliability, yield, clocking, resiliency, near-/sub-threshold, and assist schemes; Low-power analog/mixed-signal circuits for wireless, RF, MEMS, AD/DA Converters, I/O, PLLs/DLLS, imaging and DC-DC converters; Energy-efficient circuits for emerging applications (e.g., biomedical, in-vitro sensing, autonomous), circuits using emerging technologies; Cryogenic circuits. Design technology co-optimization (DTCO) for low power. 1.3. Logic and Architecture Low-power logic and microarchitecture for SoC designs, processor cores (compute, graphics, and other special purpose cores), cache, memory, arithmetic/signal processing, cryptography, variability, asynchronous design, and non-conventional computing. System technology co-optimization (STCO) for low power. 2. EDA, Systems, and Software 2.1. CAD Tools and Methodologies CAD tools, methodologies, and AI/ML-based approaches for low-power and thermal-aware design. AI/ML for acceleration of circuit simulation and IP block design convergence. Power estimation, optimization, reliability, and variation impact on power optimization at all levels of design abstraction: physical, circuit, gate, register transfer, behavior, and algorithm. 2.2. Systems and Platforms Low-power, power-aware, and thermal-aware system design including data centers, SoCs, embedded systems, Internet-of-Things (IoT), wearable computing, body-area networks, wireless sensor networks, and system-level power implications due to reliability and variability. Applications of AI/ML-based solutions and brain-inspired computing to power-aware system and platform design. 2.3. Software and Applications Energy-efficient, energy/thermal-aware software and application design, including scheduling and management, power optimization through HW/SW codesign, and emerging low-power AI/ML applications. 3. Crosscutting Topics 3.1. AI/ML Hardware Low-power AI/ML HW techniques including approximations, application driven optimizations, in-memory/energy-efficient accelerations, and neuromorphic computing; Energy-efficient AI/ML HW using emerging technologies (including quantum computing). 3.2. Hardware and System Security Low-power hardware security primitives (PUF, TRNG, cryptographic/post-quantum cryptographic accelerators), nano-electronics security, supply chain security, IoT security and AI/ML security; Energy-efficient approaches to system security. 4. Industrial Design Track ISLPED’23 solicits papers for an “Industrial Design” track to reinforce interaction between the academic research community and industry. Industrial Design track papers have the same submission deadline as regular papers and should focus on similar topics but are expected to provide a complementary perspective to academic research by focusing on challenges, solutions, and lessons learnt while implementing industrial-scale designs. Submissions (not published/accepted/under review by another journal, conference, symposium, or workshop) should be full-length papers of up to 6 pages (PDF format, double-column, US letter size, using the IEEE Conference format, available at (https://www.ieee.org/conferences/publishing/templates.html <https://www.ieee.org/conferences/publishing/templates.html>) including all illustrations, tables, references, and an abstract of no more than 250 words. Submissions must be anonymous. Submissions failing above requirements will be automatically rejected. Accepted papers will be submitted to the IEEE Xplore Digital Library and the ACM Digital Library. ISLPED’23 will present three Best Paper Awards based on the ratings of reviewers and a panel of judges. ISLPED also features a Low Power Design Contest with live demonstrations and awards. Submissions are due on May 15, 2023. More details will soon be available on the conference web page. There will be several invited talks by industry and academic thought leaders on key issues in low power electronics and design. The Symposium may also include embedded tutorials to provide attendees with the necessary background to follow recent research results, as well as panel discussions on future directions in low power electronics and design. Proposals for invited talks, embedded tutorials, and panels should be sent by email to the ISLPED’23 Technical Program Co-Chairs, Umit Ogras (uogras(a)wisc.edu <mailto:uogras@wisc.edu>) and Pascal Meinerzhagen (pascal.a.meinerzhagen(a)intel.com <mailto:pascal.a.meinerzhagen@intel.com>) by the deadline listed above. Participants interested in exhibiting at the Symposium should contact the General Co-Chairs by May 1, 2023.

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RACI: Call for Applications is now open
by Jelena Cosic 05 Jan '23

05 Jan '23

Dear colleagues, my name is Jelena, I work for the NCC as a Community Development Officer and I am taking over the role of RACI programme coordinator from my colleague Gergana Petrova. I will be available to answer any questions that you might have regarding RACI and you will see me posting announcements and other information in the upcoming months. That being said, we have an announcement to make! We are happy to share that The RIPE Academic Cooperation Initiative (RACI) is re-starting after a pause due to Covid-19 pandemic and is once again looking for talented academics in the field of Internet technology. Successful applicants receive complimentary tickets, travel and accommodation to the meetings and the opportunity to present their research. If you are working on something interesting, please apply! If you know someone in your network who is, please forward them this message. To apply submit a short abstract and draft slides via: https://www.ripe.net/raci --------------------- Application deadlines --------------------- SEE 11 (4-5 April, Split): apply by 29 January 2023 RIPE 86 (22-26 May, Rotterdam): apply by 9 March 2023 --------------------------- Examples of relevant topics --------------------------- - Network measurements and analyses - IPv6 deployment - BGP routing - Network security - Internet governance - Peering and interconnectivity - Internet of Things - Sustainability in ICT ------------------------------------------------- Get the latest news on RACI and Internet research ------------------------------------------------- - Subscribe to the RACI mailing list: https://www.ripe.net/raci/mailing-list - Join our group on LinkedIn: https://www.ripe.net/raci/linkedin Please let me know if you have any questions. Happy New Year to all! Kind regards, Jelena

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