INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN (ISLPED) 2023
--- ISLPED 2023 CALL FOR PAPERS ---
http://www.islped.org <http://www.islped.org/>, Twitter: @islped
Conference date: August 7–8, 2023
Location: TU Wien, Vienna, Austria
IMPORTANT DATES
Abstract registration: March 6, 2023, at 11:59pm PST
Full paper: March 13, 2023, at 11:59pm PST
Invited Talk, Panel, and Embedded Tutorial Proposals: April 10, 2023
Notification of Paper Acceptance: May 22, 2023
Submission of Camera-Ready Papers: June 19, 2023
The International Symposium on Low Power Electronics and Design (ISLPED) is the premier forum for presentation of innovative research in all aspects of low power electronics and design, ranging from process technologies and analog/digital circuits, simulation and synthesis tools, AI/ML-enhanced EDA/CAD, system-level design, and optimization, to system software and applications. Specific topics include, but are not limited to, the following three main tracks and sub-areas:
1. Technology, Circuits, and Architecture
1.1. Technologies
Low-power technologies for device, interconnect, logic, memory, 2.5/3D, cooling, harvesting, sensors, optical, printable, biomedical, battery, and alternative energy storage devices and technology enablers for
non-Boolean and quantum/quantum-inspired compute models.
1.2. Circuits
Low-power circuits for logic, memory, reliability, yield, clocking, resiliency, near-/sub-threshold, and assist schemes; Low-power analog/mixed-signal circuits for wireless, RF, MEMS, AD/DA Converters, I/O, PLLs/DLLS, imaging and DC-DC converters; Energy-efficient circuits for emerging applications (e.g., biomedical, in-vitro sensing, autonomous), circuits using emerging technologies; Cryogenic circuits. Design technology co-optimization (DTCO) for low power.
1.3. Logic and Architecture
Low-power logic and microarchitecture for SoC designs, processor cores (compute, graphics, and other special purpose cores), cache, memory, arithmetic/signal processing, cryptography, variability, asynchronous design, and non-conventional computing. System technology co-optimization (STCO) for low power.
2. EDA, Systems, and Software
2.1. CAD Tools and Methodologies
CAD tools, methodologies, and AI/ML-based approaches for low-power and thermal-aware design. AI/ML for acceleration of circuit simulation and IP block design convergence. Power estimation, optimization, reliability, and variation impact on power optimization at all levels of design abstraction: physical, circuit, gate, register transfer, behavior, and algorithm.
2.2. Systems and Platforms
Low-power, power-aware, and thermal-aware system design including data centers, SoCs, embedded systems, Internet-of-Things (IoT), wearable computing, body-area networks, wireless sensor networks, and system-level power implications due to reliability and variability. Applications of AI/ML-based solutions and brain-inspired computing to power-aware system and platform design.
2.3. Software and Applications
Energy-efficient, energy/thermal-aware software and application design, including scheduling and management, power optimization through HW/SW codesign, and emerging low-power AI/ML applications.
3. Crosscutting Topics
3.1. AI/ML Hardware
Low-power AI/ML HW techniques including approximations, application driven optimizations, in-memory/energy-efficient accelerations, and neuromorphic computing; Energy-efficient AI/ML HW using emerging technologies (including quantum computing).
3.2. Hardware and System Security
Low-power hardware security primitives (PUF, TRNG, cryptographic/post-quantum cryptographic accelerators), nano-electronics security, supply chain security, IoT security and AI/ML security; Energy-efficient approaches to system security.
4. Industrial Design Track
ISLPED’23 solicits papers for an “Industrial Design” track to reinforce interaction between the academic research community and industry. Industrial Design track papers have the same submission deadline as regular papers and should focus on similar topics but are expected to provide a complementary perspective to academic research by focusing on challenges, solutions, and lessons learnt while implementing industrial-scale designs.
Submissions (not published/accepted/under review by another journal, conference, symposium, or workshop) should be full-length papers of up to 6 pages (PDF format, double-column, US letter size, using the IEEE Conference format, available at (https://www.ieee.org/conferences/publishing/templates.html) including all illustrations, tables, references, and an abstract of no more than 250 words. Submissions must be anonymous. Submissions failing above requirements will be automatically rejected. Accepted papers will be submitted to the IEEE Xplore Digital Library and the ACM Digital Library. ISLPED’23 will present three Best Paper Awards based on the ratings of reviewers and a panel of judges.
ISLPED also features a Low Power Design Contest with live demonstrations and awards. Submissions are due on May 15, 2023. More details will soon be available on the conference web page.
There will be several invited talks by industry and academic thought leaders on key issues in low power electronics and design. The Symposium may also include embedded tutorials to provide attendees with the necessary background to follow recent research results, as well as panel discussions on future directions in low power electronics and design. Proposals for invited talks, embedded tutorials, and panels should be sent by email to the ISLPED’23 Technical Program Co-Chairs, Umit Ogras (uogras(a)wisc.edu <mailto:uogras@wisc.edu>) and Pascal Meinerzhagen (pascal.a.meinerzhagen(a)intel.com <mailto:pascal.a.meinerzhagen@intel.com>) by the deadline listed above.
Participants interested in exhibiting at the Symposium should contact the General Co-Chairs by May 1, 2023.

For RACI colleagues,
ACM EdgeSys'23 is calling for submissions.
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https://edge-sys.github.io/2023/
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IMPORTANT DATES
• Submission deadline: 10 March 2023
• Acceptance notification: 10 April 2023
• Camera ready: 16 April 2023
• EdgeSys date: 8 May 2023
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EdgeSys'23 aims to bring together system researchers, data scientists, engineers and practitioners to identify open directions and discuss the latest research ideas and results on edge systems, analytics and networking, especially those related to novel and emerging technologies and use cases. EdgeSys focuses on systems, analytics and networking aspects, covering system architecture, distributed ML algorithms, decentralized networking, distributed consensus and ledger techniques, edge services and data analysis.
The topics include but are not limited to the following:
• System Architecture for Edge Computing
• Serverless, In-network Computing
• Edge Storage Systems
• Distributed Machine Learning for Edge Analytics and Services
• Edge-driven Data Analytics
• Lightweight Virtualization for Edge Computing
• Distributed Consensus Algorithms and Ledger Technologies
• Infrastructure and Toolkit for Edge AI
• Trustworthy Edge AI
• Sustainable Edge Computing
• IoT Networking and Communications
• (Autonomous) Management for Edge Systems
• System Performance and Measurement
• Security and Trust Management
• Privacy-Preserving Analytics
• Data Provenance for Distributed Processing
• Heterogeneous & Scalable Orchestration
• Joint Optimization of Network, Computation and Storage Resources
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INSTRUCTIONS FOR PAPER SUBMISSION
Authors are encouraged to submit papers describing original and unpublished research, not currently under review in other venues. In particular, innovative, early-stage ideas and preliminary results are welcome. Papers must be submitted electronically as PDF files, formatted for 8.5x11-inch paper. The length of the paper must be no more than 6 pages in the ACM double-column format (10-pt font), including references and everything. Authors are suggested to use the ACM Master article template. The reviews will be single blind. The first page must contain an abstract, the name(s) and affiliation(s) of the author(s), as well as the corresponding contact information. Each submission will receive independent, blind peer reviews from the program committee. Accepted papers will be published in the ACM Digital Library. At least one of the authors of every accepted paper must register and present the paper at the workshop. The program committee will elect one paper for the Best Paper Award.
Submission: https://edgesys23.hotcrp.com/
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EdgeSys Chairs
• Aaron Ding (TU Delft, Netherlands)
• Ella Peltonen (University of Oulu, Finland)
• Volker Hilt (Nokia Bell Labs, Germany)
Steering Committee
• Jon Crowcroft (University of Cambridge, UK)
• Henning Schulzrinne (Columbia University, USA)
• Steve Uhlig (Queen Mary University of London, UK)
• Dirk Kutscher (HKUST, Hong Kong SAR)
• Dieter Kranzlmüller (University of Munich | LRZ, Germany)
• Peter Pietzuch (Imperial College London, UK)
Aaron
